In a liquid crystal display device, light transmission is controlled by alignment of liquid crystal sealed between first and second substrates, thereby displaying an image. The first substrate includes a plurality of data lines extending in a column direction, a plurality of gate lines extending in a row direction, and a plurality of thin film transistors formed near intersection parts of the pluralities of data lines and gate lines. In an in plane switching (IPS)-system liquid crystal display device, the first substrate includes a pixel electrode and a common electrode.
In the liquid crystal display device, a plurality of spacers are disposed in order to hold a distance (gap) between the first substrate and the second substrate. A seat is formed in the first substrate, a spacer is formed in the second substrate, and the first substrate and the second substrate adhere to each other such that the seat and the spacer contact with each other, thereby holding the gap. Desirably, the spacer is disposed at a position where a numerical aperture of the pixel is not degraded. For example, JP 2002-196338 A discloses a spacer disposed between two adjacent thin film transistors. Japanese unexamined patent application publication JP2009-12229A discloses a counter voltage signal line (common wiring) that is formed along a running direction of the gate line while superposed on the gate line in order to improve a numerical aperture of a pixel, the counter voltage signal line supplying a reference signal to a counter electrode (common electrode).